1. Field of the Invention
The present invention is in the field of microprocessor based computer systems, and, more particularly, is in the field of cache memory management systems for Industry Standard Architecture (ISA) compatible computer systems and other computer systems based upon the Intel.RTM. 80486 (i486.TM.) microprocessor.
2. Description of the Related Art
Industry Standard Architecture (ISA) compatible computer systems are microprocessor based computer systems based upon the Intel.RTM. 80.times.86 microprocessors (i.e., the 80286, 80386, 80386SX and 80486 microprocessors). Such ISA compatible computer systems are very well-known, and a very competitive industry has evolved to supply computer systems, peripheral components, add-in boards, software, and the like, that are based on the industry standard architecture. Other bus systems have also developed for computer systems based on the 80.times.86 family of computers. For example, the Extended Industry Standard Architecture (EISA) provides a 32-bit version of the original ISA-bus, and the Microchannel system used by IBM and others provides an alternative to the ISA-bus and the EISA-bus. Although described herein with respect to the ISA compatible computer systems, it should be understood that the disclosed invention can be used with EISA compatible computer systems and microchannel computer systems, and the like.
The original industry standard architecture was based upon the IBM.RTM. AT computer which included a so-called AT-bus, or ISA-bus, which was used to communicate between the microprocessor and a number of peripheral devices that were connected to the bus. In many systems, additional memory was included on the ISA-bus to increase the data storage capacity of the microprocessor. Because of the desire to be compatible with previously developed add-in boards, and the like, the operational speed of the ISA-bus has typically been limited to 8 or 10 MHz. More recently, many ISA compatible computer systems have included additional memory (i.e., "local memory") on a local processor bus. The local processor bus does not have the speed limitations of the ISA-bus so that the memory access times are not limited by the ISA-bus speed. However, many of the computer systems continue to include memory on the ISA-bus in addition to the local memory. In particular, memory on the ISA-bus is desirable when external devices need to have access to the memory. For example, a local area network (LAN) controller may include its own memory on the ISA-bus. Such memory is typically a dual-ported memory such that the LAN controller access the memory via one port and the microprocessor can access a second port of the memory via the ISA-bus.
As in practically all computer systems, there is a continuing goal of increasing memory capacity and memory speed in ISA compatible computer systems so as to increase the performance of the systems and allow the systems to be used with increasingly more powerful microprocessors. Increased speed and increased capacity are generally inconsistent goals since larger capacity memories tend to be slower than smaller capacity memories. Even when an ISA compatible computer system includes local memory on a local processor bus, the memory access times are generally in the 80-100 nanosecond range. Thus, many ISA compatible computer systems provide a compromise between speed and capacity by including so-called "cache memories" that have a relatively small amount of very fast memory interposed between the microprocessor and the slower main memory. Accesses to the main memory preferably are transferred through the cache memory so that the microprocessor obtains instructions and data from the cache memory. The advantage of the cache memory lies in the fact that statistically most computer programs tend to access the same group of memory locations on a repetitive basis so that once the instructions and/or data are in the cache memory, the microprocessor obtains the data from the relatively fast cache memory rather than the relatively slow main memory. (As used hereinafter, "data" will refer to both instructions and data.)
The cache memory is controlled by a cache control circuit. When the microprocessor attempts to access a memory location that is not in the cache memory, the cache control circuit swaps in a new line of data (i.e., a multiple-byte block, such as 16 or 32 bytes, for example) from main memory and swaps out an old line of data. Whether the old line of data needs to be transferred back to the main memory or simply discarded depends upon whether the cache control circuit operates the cache memory as a "write-through" cache memory or a "copy-back" cache memory. In a write-through cache memory system, data transferred from the microprocessor to the cache memory is also written to the corresponding location in the main memory so that the main memory is coherent with the cache memory. In a copy-back cache memory system, the data is initially stored only in the cache memory; however, when it is necessary to swap new data from the main memory into a cache location, the "dirty" line of data in the cache location is written to main memory. In many applications, particularly where the microprocessor is transferring a substantial amount of data to the memory and back, the copy-back cache memory system is advantageous because the stored data does not have to be transferred to the main memory until a line of data is swapped.
Recently, the Intel 80486 (i486) microprocessor has become available. The 80486 microprocessor is generally compatible with the Intel 80386 microprocessor except that the 80486 further includes, among other improvements, an internal math coprocessor and an internal 8,192-byte cache memory. The internal cache memory of the 80486 is of the write-through type that operates with 16-byte lines.
Because of the limited size of the internal cache memory, it has been found to be desirable to include an additional cache memory system external to the 80486 microprocessor that includes increased storage capacity (e.g., 128 KBytes). In addition, as discussed above, it is often desirable to have a copy-back cache.
The operating frequency of the 80486 microprocessor imposes severe constraints on an external cache memory system. An 80486 microprocessor operating at 33 MHz, for example, has a clock cycle of 30 nanoseconds. When the 80486 microprocessor places a new address on its memory address lines, it activates an address status signal (ADS#, where a "#" symbol after a signal name indicates that the signal is active low) to indicate that the addresses are valid and that a valid bus cycle has started. If a device responds with an active non-burst ready (RDY#) signal or an active burst ready signal (BRDY#) signal, within approximately 35-40 nanoseconds after ADS# is activated, the 80486 microprocessor will continue processing without delay. If neither the RDY# nor the BRDY# signal is received within 35-40 nanoseconds, the microprocessor will automatically insert 30-nanosecond wait states until one of the signals is received. In order to achieve the maximum data processing rate of the 80486 microprocessor, it is desirable to operate the 80486 without inserting any wait states when accessing an external cache memory system or any other high speed external device, such as an external coprocessor (e.g., a Weitek 4167 coprocessor).
When the 80486 generates an external address, a device addressed by the 80486 has than 10 nanoseconds (e.g., 9 nanoseconds) to determine whether the address corresponds to a cacheable address range and to return an active cache enable (KEN#) signal to the 80486. Otherwise, the data from the external device will not be cached by the microprocessor. Since it is important to the efficient operation of the microprocessor that it cache all cacheable addresses and to operate without wait states where possible, an external device should be able to respond to a memory address and generate the KEN# signal and the RDY# or BRDY# signal within the time requirements. Typically, nine nanoseconds is not a sufficient amount of time to make such a determination.